>>

Séminaire ASTRE : Raoul Velazco

Titre du séminaire et orateur

Error-rate prediction for programmable circuits: methodology, tools and studied-cases.

Raoul Velazco, TIMA, Grenoble.

Date et lieu

Jeudi 3 mai 2018, 10h30.

ENSEA, salle 384.

Abstract

The evaluation of the sensitivity to SEU (Single Event Upsets) of programmable integrated circuits (microprocessors, FPGAs, digital signal processors, …) is generally based on data obtained “on-line” from test campaigns performed in suitable facilities such as cyclotrons, linear accelerators, … During these experiments the tested circuit is exposed to selected particle beams (heavy ions, protons, neutrons) while it executes a given application. In this presentation will be presented a method combining the results issued from radiation ground test experiments with those issued from fault injection sessions (performed off beam) allowing the prediction of the error rates for any application without the need for exposing the target circuit to radiation during its execution.

Bio

Raoul VELAZCO was born in Montevideo (Uruguay) in 1952. He received the Diplomas of Engineer, PhD and Dr. ès Sciences from Institut Polytechnique de Grenoble, respectively in 1979, 1982 and 1990. Since 1984 he is a researcher of the CNRS, the French Research Agency. He leads the RIS (Reliable Integrated Systems) at TIMA Labs. (Grenoble). His researches concern the methodology to asses the sensitivity to the effects of radiation of integrated circuits and systems, the potential solutions to deal with these effects and related experiments in particle accelerator facilities and in scientific satellites.

Retour