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Séminaire ASTRE : Syed Zahid Ahmed

Titre du séminaire et orateur

Xilinx VivadoHLS tools overview and potentials.
Syed Zahid AHMED (ETIS, UMR-8051 ENSEA/CNRS/UCP).

Date et lieu

Mardi 26 février 2013, 14-16h.
ENSEA, salle 3xx.

Summary

Field Programmable Gate Arrays (FPGAs) are widely used as prototyping or actual SoC implementation for signal processing applications. Their massive parallelism and availability of abundant heterogeneous blocks of on-chip memory and DSP building block components allow efficient implementation which often rivals standard PCs, DSPs and GPUs. With the emergence of 28nm SoC FPGAs from Xilinx and Altera with hard ARM processor, the FPGAs have become further attractive for embedded systems, bringing the marriage of CPU and Programmable-Logic for heterogeneous computing and strengthening the move towards IP-based or System-Level design.

FPGAs despite their numerous attractive properties have suffered from their programming complexity issue compared to processors. Since FPGAs from the beginning were designed/intended to implement or prototype ASICs on a programmable platform, naturally RTLs (VHDL, Verilog etc.) were inherently the best choice to program them. This served as powerful tool and weapon for FPGAs in the 90s and early 2000s to foster their growth and adoption against competing solutions by using in-house and 3rd party industry standard RTL tools. However as FPGAs dramatically increased in their logic densities during last decade by aggressively following the Moore's law, design productivity also became a critical issue. Over the years FPGAs designs have grown to more IP-centric like SoCs/ASICs to exploit the natural benefits of reusability, fast time to market. Furthermore move to Hard-ARM based FPGAs will further strengthen this trend by bringing strong IP ecosystem of ARM processor for SoCs/ASICs/ASSPs to FPGAs. In addition to that both of the FPGA leaders are undertaking substantial R&D on the programmability problem of FPGAs. Xilinx has adopted the ESL (Electronic System Level) wave and Altera is investigating use of OpenCL for FPGA programming. ESL or more formally known as HLS (High Level Synthesis) has remained a topic of significant interest in industry and academic research for a long time and finally in late 2000s it has gained momentum with industrial success by the availability of the state of the art tools. Surprisingly, as FPGAs have historically eased several aspects for designers and research community, they have also played a significant role for ESL tools. Xilinx has created a ground up next-generation tool Vivado which also incorporates built-in ESL tools (former AutoESL) for C/C++/SystemC to HDL transformation.

This Seminar is devoted to Xilinx Vivado HLS tools and is divided in to two parts.

  1. Part-1: Presentation

    It will start with brifly providing a historical overview of ESL tools failures and success waves in industry and academic research since 90s. This will also highlight the key factors that led to historic rise of FPGAs vs several competing reconfigurable computing solutions which were doomed by their custom HLS compilers and languages. We will discover current state of the art ESL/HLS tools available from leading EDA vendors with their differentiation from each other and former solutions. Then the Xilinx Vivado and VivadoHLS tools suite will be discussed in detail. We will discuss tool flows, their compatibility with Xilinx tools (ISE/XPS/System Generator). The strength and weakness of these tools will be highlighted. The potentials of the tools for research in application domains such as image/video processing, medical imaging, floating point computation will be discussed. We will discuss briefly the image processing IPs research done in ETIS lab in industrial project with SagemCom and our experience using these HLS tools. Finally some small examples/interactive videos will be shown to provide practical overview of the tools.

  2. Part-2: Demos and Exercies (Salle Arch. 362)

    This part is for practical hands-on experience with the tools. A demo of complex application done using VivadoHLS running on Virtex6 FPGA will be shown. Then participants will use the tools for a simple FIR application to get familiar with the tools.

Prerequisite

  • Fundamentals of HW design and FPGAs
  • Fundamentals of Xilinx/Altera tools

Language

English (Presentation), French/English (Q&A Part1, Part-2)

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