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Séminaire ETIS : Raoul Velazco

Titre du séminaire et orateur

Error rate prediction of complex digital architectures: methodology, tools and studied cases.

Raoul Velazco, directeur de recherche CNRS, TIMA Grenoble.

Date et lieu

Mardi 3 mai 2016, 11h.

ENSEA, salle du conseil.

Abstract

The evaluation of the sensitivity to SEU (Single Event Upsets) of programmable integrated circuits (microprocessors, FPGAs, digital signal processors, …) is generally based on data obtained “on-line” from test campaigns performed in suitable facilities such as cyclotrons, linear accelerators, … During these experiments the tested circuit is exposed to selected particle beams (heavy ions, protons, neutrons) while it executes a given application. In this presentation will be presented a method combining the results issued from radiation ground test experiments with those issued from fault injection sessions (performed off beam) allowing the prediction of the error rates for any application without the need for exposing the target circuit to radiation during its execution.

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