Séminaire ICI : Bane Vasic
Titre du séminaire et orateur
Date et lieu
Mardi 19 mai, 14h00.
ENSEA Cergy-Pontoise, salle 384.
In this talk we discuss an improved version of probabilistic gradient descent bit flipping algorithm for decoding low density parity check codes, based on MUltiple Decoding attempts and Random re-Initializations (MUDRI). The proposed algorithm significantly increases the probability of correcting error patterns uncorrectable by the existing variants of bit-flipping algorithm.
The performance of the algorithm implemented in noisy hardware will be presented for various code types and codeword lengths. We will show that it is superior to other hard decision algorithms. The MUDRI decoder is mostly insensitive to the failures in registers and logic gates and therefore represents a desirable solution for implementation in unreliable hardware.
Bane Vasić is a Professor of Electrical and Computer Engineering and Mathematics at the University of Arizona, and a Director of the Error Correction Laboratory.
He is an inventor of the soft error-event decoding algorithm, and the key architect of a detector/decoder for Bell Labs hard drive read channel chips which were regarded as the best in industry. Different variants of this algorithm were implemented in virtually all magnetic hard drives. His pioneering work on structured low-density parity check (LDPC) error correcting codes and invention of codes has enabled low-complexity iterative decoder implementations.
Dr. Vasic currently serves as a Member of the Editorial Board of the IEEE Transactions on Magnetics and Guest Editor of three JSAC Special Issues on Data Storage Channels. He is an IEEE Fellow, and a Chair of the IEEE Data Storage Technical Committee.