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Séminaires ICI

Date et lieu des séminaires

Mercredi 5 décembre 2012, 14h30.
ENSEA, salle 384.

Fault-tolerant Min-Sum decoder running on faulty hardware

Christiane Kameni Ngassa, ETIS, équipe ICI.

This work is concerned with the design of fault-tolerant decoder architectures for binary LDPC codes, able to provide efficient error protection even if they operate on faulty hardware. This is a completely new paradigm in coding theory, as it was traditionally assumed that the operations of an error correction decoder are deterministic and that the randomness (in the form of noise and/or errors) exists only in the transmission channel. In the first part, we investigate the behavior of Min-Sum-based decoders running on circuits made of probabilistic components. Simple error models are used to describe the probabilistic behavior of the arithmetic operators used by the Min-Sum decoder. We then evaluate the impact of various error models on the decoder's performance and show that in most cases the Self-Corrected Min-Sum decoder is robust to such a probabilistic behavior. In the second part, we deal with imprecise arithmetic operators. Such arithmetic operators have a deterministic behavior, but they may output a wrong result. Imprecise arithmetic is usually obtaining by pruning some of the components of the exact operator, in order to decrease the energy consumption of the circuit. We investigate the impact of imprecise operators on both the performance and the energy consumption of several Min-Sum-based decoders.

Performance Bounds for Spatially-Coupled LDPC Codes over the Block Erasure Channel

Iryna Andriyanova, ETIS, équipe ICI.

Here, we derive upper and lower bounds on the decoding performance of spatially-coupled LDPC codes, assuming the transmission over the block erasure channel. Although relatively simple, the bounds catch well the decay of the erasure probability after decoding when the block erasure probability decreases. The presented result can be further extended to block-fading transmission channels.

Rewriting Codes for Flash Memories

Paul H. Siegel, University of California, San Diego.

We consider binary and non-binary rewriting codes for flash emories. These codes can extend the lifetime of a flash memory by postponing the need for block erase operations. We will review several constructions of rewriting codes for single-level cell memories (one bit per cell) and multi-level cell memories (two or more bits per cell), and we discuss their efficiency with respect to theoretical sum-rate limits. Both unrestricted-rate codes – in which the rates used on different writes need not be the same – and fixed rate codes – in which all writes have the same rate – will be considered. We then invoke the “continuous approximation” to determine the optimal write regions for lattice-based, multi-level rewriting codes in the asymptotic case of a continuum of cell levels. These write regions are then used to guide the construction of t-write codes for n cells that support q discrete levels. For the special case of two cells, we present a general encoding scheme for practical t-write codes. We then discuss the problem of finding consistent message-to-codeword assignments when the number of cells is more than two.

This is joint work with Aman Bhatia, Aravind Iyengar, Minghai Qin, and Brian Kurkoski.

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