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Séminaire ETIS : Maurizio Palesi

Titre du séminaire et orateur

Network-on-chip (NoC) architectures.

Maurizio Palesi (Université de Catane, Italie)

Date et lieu

Mardi 10 juillet 2018, 15h.

ENSEA, salle 331

Abstract

The aim the talk is presenting my research contributions in the context of network-on-chip (NoC) architectures. I will cover four main topics, including, routing algorithms, mapping techniques, data encoding, and approximate communication. Specifically, a methodology for designing application specific routing algorithms will be presented. In this context, emphasis will be devoted on a set of selection policies aimed at i) managing partially faulty links and ii) improving the adaptivity of multi-path routing algorithms. A multi-objective design space exploration technique aimed at optimizing the power vs. performance trade-off by exploring the mapping and the routing design spaces will be presented. Finally, two main techniques aimed at improving the energy efficiency of NoC based systems will be introduced. The first one, is based on data encoding for minimizing the switching activity of the NoC links. The second one extends the approximate computing paradigm to the communication sub-system with the aim of trading-off communication energy efficiency with the quality of the application outputs.

Bio

Maurizio Palesi is Associate Professor in Computer Engineering at the Department of Electrical, Electronics and Computer Engineering, Università degli Studi di Catania, Catania, Italy. His research activity is focused in the area of embedded systems with particular emphasis on single-chip implementations based on the network-on-chip design paradigm. He is co-author of 50 papers in international journals, 6 book chapters, 70 papers in international conferences/symposium/workshops, and co-author of a book. He has been recipient of the best paper award at the Design Automation and Test in Europe (DATE 2011) and the HiPEAC paper award 2014. Dr. Palesi has served as Guest Editor of 17 special issues in top-level journals, including, IET Computers & Digital Techniques, ACM Transactions on Embedded Computing Systems, International Journal of High Performance Systems Architecture. He has served as General Chair and TPC Co-Chair in several international conferences and workshops. He serves as Associate Editor in 12 international journals.

He is member of the European Network on High Performance and Embedded Architecture and Compilation (HiPEAC) and IEEE Senior Member.

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